TEDGPL=0, TMOD=000, TCK=others
AGT Mode Register 1
| TMOD | AGT operating mode select 0 (others): Setting prohibited 0 (000): Timer mode 1 (001): Pulse output mode 2 (010): Event counter mode 3 (011): Pulse width measurement mode 4 (100): Pulse period measurement mode |
| TEDGPL | AGTIO edge polarity select 0 (0): Single-edge 1 (1): Both-edge |
| TCK | AGT count source select 0 (000): PCLKB 0 (others): Setting prohibited 1 (001): PCLKB/8 3 (011): PCLKB/2 4 (100): Divided clock LOCO specified by bits CKS[2:0] in the AGTMR2 register 5 (101): Underflow event signal from AGT0 6 (110): Divided clock fSUB specified by bits CKS[2:0] in the AGTMR2 register |
| Reserved | This bit is read as 0. The write value should be 0. |